The present invention relates generally to data processing systems, and more specifically to handling overflow from registers.
As known to those skilled in the art, in central processing unit (“CPU”) architectures, registers are used to temporarily store and manipulate values using arithmetic instructions. Coded instructions to be executed on the CPU, and which may store and manipulate values on the registers and read values from the registers, must first be compiled. During a typical compilation process, a compiler is free to use a virtually unlimited number of symbolic registers. At the tail end of a compilation process, a register allocator may be used to map the symbolic registers onto the real, architected registers. When there are too many symbolic registers to be allocated to the real registers in a cycle, the overflow of symbolic registers may be temporarily stored in memory. This overflow to memory is commonly known as “spilling”, and the location to which the overflow is made may be referred to as a “spill”. To accomplish this spilling to memory, a register allocator will insert a store to spill (“store”) instruction in a “spill code”. When the stored data is needed again, the register allocator inserts a load from spill (“load”) instruction in the “spill code” to load the symbolic register back into an available register location. (“Spill code” typically may be found dispersed within a larger body of processor code commonly known as “procedure code”.)
While spilling designs for single registers are well known, effective designs for a CPU architecture having parallel registers are less apparent. A new design for handling the storing and loading of spills in a CPU architecture having parallel registers would be desirable.